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Suhas Shivapakash
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1

Energy efficient hardware architectures for memory prohibit..:

Shivapakash, Suhas , 2024
Link: https://nbn-resolving.de..
 
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2

FantastIC4: A Hardware-Software Co-Design Approach for Effi..:

Wiedemann, Simon ; Shivapakash, Suhas ; Becking, Daniel...
IEEE Open Journal of Circuits and Systems.  2 (2021)  - p. 407-419 , 2021
Link: https://doi.org/10.1109/..
 
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3

A Power Efficiency Enhancements of a Multi-Bit Accelerator ..:

Shivapakash, Suhas ; Jain, Hardik ; Hellwich, Olaf.
IEEE Open Journal of Circuits and Systems.  2 (2021)  - p. 156-169 , 2021
Link: https://doi.org/10.1109/..
 
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4

A Power Efficient Multi-Bit Accelerator for Memory Prohibit..:

, In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS),
Shivapakash, Suhas ; Jain, Hardik ; Hellwich, Olaf. - p. 1-5 , 2020
Link: https://doi.org/10.1109/..
 
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5

FantastIC4: A Hardware-Software Co-Design Approach for Effi..:

Simon Wiedemann ; Suhas Shivapakash ; Daniel Becking...
https://ieeexplore.ieee.org/document/9440253/.  , 2021
Link: https://doi.org/10.1109/..
 
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6

A Power Efficiency Enhancements of a Multi-Bit Accelerator ..:

Suhas Shivapakash ; Hardik Jain ; Olaf Hellwich.
https://ieeexplore.ieee.org/document/9335311/.  , 2021
Link: https://doi.org/10.1109/..
 
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7

FantastIC4: A Hardware-Software Co-Design Approach for Effi..:

Wiedemann, Simon ; Shivapakash, Suhas ; Wiedemann, Pablo...
http://arxiv.org/abs/2012.11331.  , 2020
Link: http://arxiv.org/abs/201..
 
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