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Proceedings of the 2020 on Great Lakes Symposium on VLSI ,
4
Design Automation Methodology from RTL to Gate-level Netlis..:
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2019 IEEE International Superconductive Electronics Conference (ISEC) ,
5
Logic Design of a 16-bit Bit-Slice Shifter for 64-bit RSFQ ..:
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2019 IEEE International Superconductive Electronics Conference (ISEC) ,
6
Design of Datapath Circuits for a Bit-Parallel 8-bit RSFQ M..:
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2019 IEEE International Superconductive Electronics Conference (ISEC) ,
7
An 8-bit Bit-Slice TEA-Cryptographic Accelerator for 64-bit..:
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2019 IEEE International Superconductive Electronics Conference (ISEC) ,
8