I agree that this site is using cookies. You can find further informations here.
X
Tikekar, Mehul
11  results:
Search for persons X
?
1

Memory-Hierarchical and Mode-Adaptive HEVC Intra Prediction..:

Huang, Chao-Tsung ; Tikekar, Mehul ; Chandrakasan, Anantha P.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  22 (2014)  7 - p. 1515-1525 , 2014
Link: https://doi.org/10.1109/..
 
?
2

Technique for Efficient Evaluation of SRAM Timing Failure:

Qazi, Masood ; Tikekar, Mehul ; Dolecek, Lara..
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  21 (2013)  8 - p. 1558-1562 , 2013
Link: https://doi.org/10.1109/..
 
?
3

Loop flattening & spherical sampling : highly efficient ..:

, In: Proceedings of the Conference on Design, Automation and Test in Europe,
Qazi, Masood ; Tikekar, Mehul ; Dolecek, Lara.. - p. 801-806 , 2010
Link: https://dl.acm.org/doi/1..
 
?
4

Low-Rank Training of Deep Neural Networks for Emerging Memo..:

Gural, Albert ; Nadeau, Phillip ; Tikekar, Mehul.
http://arxiv.org/abs/2009.03887.  , 2020
Link: http://arxiv.org/abs/200..
 
?
5

A Fully Integrated Energy-Efficient H.265/HEVC Decoder With..:

Tikekar, Mehul ; Sze, Vivienne ; Chandrakasan, Anantha P
10.1109/JSSC.2018.2837124.  , 2019
Link: https://hdl.handle.net/1..
 
?
6

Energy-efficient video decoding using data statistics:

Tikekar, Mehul (Mehul Deepak)
http://hdl.handle.net/1721.1/113990.  , 2017
Link: http://hdl.handle.net/17..
 
?
7

A Fully-Integrated Energy-Efficient H.265/HEVC Decoder with..:

Tikekar, Mehul ; Sze, Vivienne ; Chandrakasan, Anantha P
http://www.vlsisymposium.org/files/VLSI2017_Circ_program.pdf?170531.  , 2017
Link: http://hdl.handle.net/17..
 
?
8

Decoder Hardware Architecture for HEVC:

Tikekar, Mehul ; Huang, Chao-Tsung ; Sze, Vivienne..
http://dx.doi.org/10.1007/978-3-319-06895-4_10.  , 2014
Link: http://hdl.handle.net/17..
 
?
9

A 249Mpixel/s HEVC video-decoder chip for Quad Full HD appl..:

Huang, Chao-Tsung ; Tikekar, Mehul ; Juvekar, Chiraag Shashikant..
http://dx.doi.org/10.1109/ISSCC.2013.6487682.  , 2013
Link: http://hdl.handle.net/17..
 
?
10

A 249-Mpixel/s HEVC Video-Decoder Chip for 4K Ultra-HD Appl..:

Tikekar, Mehul ; Huang, Chao-Tsung ; Sze, Vivienne..
http://dx.doi.org/10.1109/jssc.2013.2284362.  , 2013
Link: http://hdl.handle.net/17..
 
?
11

Technique for Efficient Evaluation of SRAM Timing Failure:

Qazi, Masood ; Tikekar, Mehul ; Dolecek, Lara..
http://dx.doi.org/10.1109/tvlsi.2012.2212254.  , 2012
Link: http://hdl.handle.net/17..
 
1-11