Touba, Nur A
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2

Highly Efficient Layered Syndrome-based Double Error Correc..:

, In: 2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT),
 
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5

Selective Checksum based On-line Error Correction for RRAM ..:

, In: 2020 IEEE 38th VLSI Test Symposium (VTS),
Das, Abhishek ; Touba, Nur A. - p. 1-6 , 2020
 
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6

A New Class of Single Burst Error Correcting Codes with Par..:

Das, Abhishek ; Touba, Nur A.
IEEE Transactions on Computers.  69 (2020)  2 - p. 253-259 , 2020
 
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7

Low Complexity Burst Error Correcting Codes to Correct MBUs..:

, In: Proceedings of the 2018 Great Lakes Symposium on VLSI,
Das, Abhishek ; Touba, Nur A. - p. 219-224 , 2018
 
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8

Reducing control bit overhead for X-masking/X-canceling hyb..:

, In: Proceedings of the 53rd Annual Design Automation Conference,
 
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9

Reducing Cost of Yield Enhancement in 3-D Stacked Memories ..:

Rab, Muhammad Tauseef ; Bawa, Asad Amin ; Touba, Nur A.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  22 (2014)  9 - p. 2017-2024 , 2014
 
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10

Improved Trace Buffer Observation via Selective Data Captur..:

Yang, Joon-Sung ; Touba, Nur A.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  21 (2013)  2 - p. 320-328 , 2013
 
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11

Correlation-Based Rectangular Encoding:

Lee, Jinkyu ; Touba, Nur A.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  18 (2010)  10 - p. 1483-1492 , 2010
 
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12

Fundamentals of CMOS design:

, In: Electronic Design Automation,
Chen, Xinghao ; Touba, Nur A. - p. 39-95 , 2009
 
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13

System-on-chip test architectures 

nanometer design for testability  The Morgan Kaufmann series in systems on silicon
Copies:  Zentrale:E02 a inf 170 ef/741
 
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14

Low-Power Testing:

, In: System-on-Chip Test Architectures,
Girard, Patrick ; Wen, Xiaoqing ; Touba, Nur A. - p. 307-350 , 2008
 
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15

Guest Editorial:

Touba, Nur ; Salsano, Adelio ; Choi, Minsu
Journal of Electronic Testing.  24 (2008)  1-3 - p. 9-10 , 2008
 
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