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Udupa, Pramod
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1

IKW: Inter-Kernel Weights for Power Efficient Edge Computin:

Udupa, Pramod ; Mahale, Gopinath ; Chandrasekharan, Kiran Kolar.
IEEE Access.  8 (2020)  - p. 90450-90464 , 2020
Link: https://doi.org/10.1109/..
 
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2

Accelerating Depthwise Convolution and Pooling Operations o..:

, In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS),
Udupa, Pramod ; Mahale, Gopinath ; Chandrasekharan, Kiran Kolar. - p. 1-5 , 2020
Link: https://doi.org/10.1109/..
 
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3

Low Complexity, Parallel Algorithms, and Scalable Architect..:

Udupa, Pramod
tel-01099824.  , 2014
Link: https://inria.hal.scienc..
 
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4

Low Complexity, Parallel Algorithms, and Scalable Architect..:

Udupa, Pramod
tel-01099824.  , 2014
Link: https://hal.inria.fr/tel..
 
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5

Low Complexity, Parallel Algorithms, and Scalable Architect..:

Udupa, Pramod
tel-01099824.  , 2014
Link: https://inria.hal.scienc..
 
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6

Algorithmes parallèles et architectures évolutives de faibl..:

Udupa, Pramod
http://www.theses.fr/2014REN1S039/document.  , 2014
Link: http://www.theses.fr/201..
 
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7

Low Complexity, Parallel Algorithms, and Scalable Architect..:

Udupa, Pramod
tel-01099824.  , 2014
Link: https://inria.hal.scienc..
 
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8

A Novel Hierarchical Low Complexity Synchronization Method ..:

Udupa, Pramod ; Sentieys, Olivier ; Scalart, Pascal
info:eu-repo/semantics/altIdentifier/doi/10.1109/VTCSpring.2013.6691838.  , 2013
Link: https://inria.hal.scienc..
 
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9

Design and Implementation of DSP algorithms for 100 Gbps Co..:

Udupa, Pramod ; Sentieys, Olivier ; Bramerie, Laurent
hal-00931542.  , 2013
Link: https://inria.hal.scienc..
 
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10

Design and Implementation of DSP algorithms for 100 Gbps Co..:

Udupa, Pramod ; Sentieys, Olivier ; Bramerie, Laurent
hal-00931542.  , 2013
Link: https://hal.inria.fr/hal..
 
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11

A Block-Parallel Architecture for Initial and Fine Synchron..:

Udupa, Pramod ; Sentieys, Olivier ; Scalart, Pascal
info:eu-repo/semantics/altIdentifier/doi/10.1109/ICC.2013.6655326.  , 2013
Link: https://inria.hal.scienc..
 
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12

Design and Implementation of DSP algorithms for 100 Gbps Co..:

Udupa, Pramod ; Sentieys, Olivier ; Bramerie, Laurent
hal-00931542.  , 2013
Link: https://inria.hal.scienc..
 
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13

A Novel Hierarchical Low Complexity Synchronization Method ..:

Udupa, Pramod ; Sentieys, Olivier ; Scalart, Pascal
info:eu-repo/semantics/altIdentifier/doi/10.1109/VTCSpring.2013.6691838.  , 2013
Link: https://inria.hal.scienc..
 
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14

Design and Implementation of DSP algorithms for 100 Gbps Co..:

Udupa, Pramod ; Sentieys, Olivier ; Bramerie, Laurent
hal-00931542.  , 2013
Link: https://inria.hal.scienc..
 
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15

A Novel Hierarchical Low Complexity Synchronization Method ..:

Udupa, Pramod ; Sentieys, Olivier ; Scalart, Pascal
info:eu-repo/semantics/altIdentifier/doi/10.1109/VTCSpring.2013.6691838.  , 2013
Link: https://hal.inria.fr/hal..
 
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