E-LIB Suche - Ergebnisse für: Verhelst, Marian

1

Optimizing Layer-Fused Scheduling of Transformer Networks o..:

, In: 2024 25th International Symposium on Quality Electronic Design (ISQED),

Colleman, Steven ; Symons, Arne ; Jung, Victor J.B.. - p. 1-6 , 2024

Link: https://doi.org/10.1109/..

2

Enabling Efficient Hardware Acceleration of Hybrid Vision T..:

, In: 2024 IEEE International Symposium on Circuits and Systems (ISCAS),

Dumoulin, Joren ; Houshmand, Pouya ; Jain, Vikram. - p. 1-5 , 2024

Link: https://doi.org/10.1109/..

3

Towards Heterogeneous Multi-core Systems-on-Chip for Edge M..:

Jain, Vikram ; Verhelst, Marian - 1st ed. 2024 . , 2024

Link: https://doi.org/10.1007/..

4

Optimization of block-scaled integer GeMMs for efficient DN..:

Satya Murthy, Nitish ; Catthoor, Francky ; Verhelst, Marian
Journal of Systems Architecture. 154 (2024) - p. 103236 , 2024

Link: https://doi.org/10.1016/..

5

BitWave: Exploiting Column-Based Bit-Level Sparsity for Dee..:

, In: 2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA),

Shi, Man ; Jain, Vikram ; Joseph, Antony.. - p. 732-746 , 2024

Link: https://doi.org/10.1109/..

6

A 96-Channel 40nm CMOS Potentiostat for Parallel Experiment..:

Li, Peishuo ; Molderez, Tom R. ; Villamor, David H...
IEEE Transactions on Circuits and Systems I: Regular Papers. 70 (2023) 1 - p. 114-127 , 2023

Link: https://doi.org/10.1109/..

7

[Errata]:

Verhelst, Marian
IEEE Solid-State Circuits Magazine. 15 (2023) 1 - p. 71-71 , 2023

Link: https://doi.org/10.1109/..

8

Conclusions and Future Work:

, In: Efficient Execution of Irregular Dataflow Graphs,

Shah, Nimish ; Meert, Wannes ; Verhelst, Marian - p. 125-129 , 2023

Link: https://doi.org/10.1007/..

9

PATRONoC: Parallel AXI Transport Reducing Overhead for Netw..:

, In: 2023 60th ACM/IEEE Design Automation Conference (DAC),

Jain, Vikram ; Cavalcante, Matheus ; Bruschi, Nazareno... - p. 1-6 , 2023

Link: https://doi.org/10.1109/..

10

Irregular Workloads at Risk of Losing the Hardware Lottery:

, In: Efficient Execution of Irregular Dataflow Graphs,

Shah, Nimish ; Meert, Wannes ; Verhelst, Marian - p. 1-21 , 2023

Link: https://doi.org/10.1007/..

11

Scoping the Landscape of (Extreme) Edge Machine Learning Pr..:

, In: Towards Heterogeneous Multi-core Systems-on-Chip for Edge Machine Learning,

Jain, Vikram ; Verhelst, Marian - p. 43-57 , 2023

Link: https://doi.org/10.1007/..

12

Networks-on-Chip to Enable Large-Scale Multi-core ML Accele..:

, In: Towards Heterogeneous Multi-core Systems-on-Chip for Edge Machine Learning,

Jain, Vikram ; Verhelst, Marian - p. 143-161 , 2023

Link: https://doi.org/10.1007/..

13

CMDS: Cross-layer Dataflow Optimization for DNN Accelerator..:

, In: 2023 24th International Symposium on Quality Electronic Design (ISQED),

Shi, Man ; Colleman, Steven ; VanDeMieroop, Charlotte... - p. 1-8 , 2023

Link: https://doi.org/10.1109/..

14

DAG Processing Unit Version 1 (DPU): Efficient Execution of..:

, In: Efficient Execution of Irregular Dataflow Graphs,

Shah, Nimish ; Meert, Wannes ; Verhelst, Marian - p. 69-88 , 2023

Link: https://doi.org/10.1007/..

15

TinyVers: A Tiny Versatile System-on-Chip With State-Retent..:

Jain, Vikram ; Giraldo, Sebastian ; Roose, Jaro De...
IEEE Journal of Solid-State Circuits. 58 (2023) 8 - p. 2360-2371 , 2023

Link: https://doi.org/10.1109/..