Verreck, Devin
25  results:
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1

Modeling the Operation of Charge Trap Flash Memory—Part II:..:

Verreck, Devin ; Schanovsky, Franz ; Arreghini, Antonio...
IEEE Transactions on Electron Devices.  71 (2024)  1 - p. 554-559 , 2024
 
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2

The Impact of IGZO Channel Composition on DRAM Transistor P..:

Kruv, Anastasiia ; Van Setten, M. J. ; Dekkers, Hendrik F. W....
IEEE Transactions on Electron Devices.  70 (2023)  9 - p. 4674-4679 , 2023
 
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3

The Promise of 2-D Materials for Scaled Digital and Analog ..:

, In: 2023 IEEE International Solid- State Circuits Conference (ISSCC),
 
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5

Electrolithic Memory: A New Device for Ultrahigh-Density Da..:

Fransen, Senne ; Willems, Kherim ; Philipsen, Harold...
IEEE Transactions on Electron Devices.  69 (2022)  5 - p. 2377-2383 , 2022
 
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6

Dual gate synthetic MoS2 MOSFETs with 4.56µF/cm2 channel ca..:

, In: 2021 IEEE International Electron Devices Meeting (IEDM),
Wu, Xiangyu ; Cott, Daire ; Lin, Zaoyang... - p. 7.4.1-7.4.4 , 2021
 
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7

Cyclic Thermal Effects on Devices of Two‐Dimensional Layere..:

Kim, Yeonsu ; Kaczer, Ben ; Verreck, Devin...
Advanced Electronic Materials.  7 (2021)  9 - p. 2100348 , 2021
 
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8

Scaling of double-gated WS2 FETs to sub-5nm physical gate l..:

, In: 2021 IEEE International Electron Devices Meeting (IEDM),
Smets, Quentin ; Schram, Tom ; Verreck, Devin... - p. 34.2.1-34.2.4 , 2021
 
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10

Ultra-scaled MOCVD MoS2 MOSFETs with 42nm contact pitch and..:

, In: 2019 IEEE International Electron Devices Meeting (IEDM),
Smets, Quentin ; Groven, Benjamin ; Caymax, Matty... - p. 23.2.1-23.2.4 , 2019
 
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11

Device and Circuit Level Gate Configuration Optimization fo..:

, In: 2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD),
 
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