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Wijeratne, Sasindu
22  results:
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1

Sparse MTTKRP Acceleration for Tensor Decomposition on GPU:

, In: Proceedings of the 21st ACM International Conference on Computing Frontiers,
Wijeratne, Sasindu ; Kannan, Rajgopal ; Prasanna, Viktor - p. 88-96 , 2024
Link: https://dl.acm.org/doi/1..
 
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2

Exploiting On-Chip Heterogeneity of Versal Architecture for..:

, In: 2023 33rd International Conference on Field-Programmable Logic and Applications (FPL),
Chen, Paul ; Manjunath, Pavan ; Wijeratne, Sasindu.. - p. 219-227 , 2023
Link: https://doi.org/10.1109/..
 
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3

Dynasor: A Dynamic Memory Layout for Accelerating Sparse MT..:

, In: 2023 IEEE 35th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD),
Wijeratne, Sasindu ; Kannan, Rajgopal ; Prasanna, Viktor - p. 23-33 , 2023
Link: https://doi.org/10.1109/..
 
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4

Accelerating Sparse MTTKRP for Tensor Decomposition on FPGA:

, In: Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays,
Wijeratne, Sasindu ; Wang, Ta-Yang ; Kannan, Rajgopal. - p. 259-269 , 2023
Link: https://dl.acm.org/doi/1..
 
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5

How can Human-in-the-loop Improve the Performance of SAR AT..:

, In: 2023 IEEE International Radar Conference (RADAR),
Zhang, Bingyi ; Wijeratne, Sasindu ; Ye, Tian... - p. 1-6 , 2023
Link: https://doi.org/10.1109/..
 
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6

Performance Modeling Sparse MTTKRP Using Optical Static Ran..:

, In: 2022 IEEE High Performance Extreme Computing Conference (HPEC),
Wijeratne, Sasindu ; Jaiswal, Akhilesh ; Jacob, Ajey P... - p. 1-7 , 2022
Link: https://doi.org/10.1109/..
 
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7

Estimating the Impact of Communication Schemes for Distribu..:

, In: 2022 21st International Symposium on Parallel and Distributed Computing (ISPDC),
Ye, Tian ; Kuppannagari, Sanmukh R. ; De Rose, Cesar A. F.... - p. 49-56 , 2022
Link: https://doi.org/10.1109/..
 
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8

Modeling the Energy Efficiency of GEMM using Optical Random..:

, In: 2022 IEEE High Performance Extreme Computing Conference (HPEC),
Zhang, Bingyi ; Jaiswal, Akhilesh ; Mathew, Clynn... - p. 1-7 , 2022
Link: https://doi.org/10.1109/..
 
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9

Reconfigurable Low-latency Memory System for Sparse Matrici..:

, In: 2021 IEEE High Performance Extreme Computing Conference (HPEC),
Wijeratne, Sasindu ; Kannan, Rajgopal ; Prasanna, Viktor - p. 1-7 , 2021
Link: https://doi.org/10.1109/..
 
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10

A High Throughput Parallel Hash Table on FPGA using XOR-bas..:

, In: 2020 IEEE High Performance Extreme Computing Conference (HPEC),
Zhang, Ruizhi ; Wijeratne, Sasindu ; Yang, Yang.. - p. 1-7 , 2020
Link: https://doi.org/10.1109/..
 
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11

Scalable High Performance SDN Switch Architecture on FPGA f..:

, In: Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays,
Wijeratne, Sasindu ; Ekanayake, Ashen ; Jayaweera, Sandaruwan.. - p. 117 ff. , 2019
Link: https://dl.acm.org/doi/1..
 
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12

PAHD: Perception-Action based Human Decision Making using E..:

Wijeratne, Sasindu ; Zhang, Bingyi ; Kannan, Rajgopal..
http://arxiv.org/abs/2401.02687.  , 2024
Link: http://arxiv.org/abs/240..
 
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13

Graph Neural Network for Accurate and Low-complexity SAR AT:

Zhang, Bingyi ; Wijeratne, Sasindu ; Kannan, Rajgopal..
http://arxiv.org/abs/2305.07119.  , 2023
Link: http://arxiv.org/abs/230..
 
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14

Dynasor: A Dynamic Memory Layout for Accelerating Sparse MT..:

Wijeratne, Sasindu ; Kannan, Rajgopal ; Prasanna, Viktor
http://arxiv.org/abs/2309.09131.  , 2023
Link: http://arxiv.org/abs/230..
 
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15

Exploiting On-chip Heterogeneity of Versal Architecture for..:

Chen, Paul ; Manjunath, Pavan ; Wijeratne, Sasindu..
http://arxiv.org/abs/2308.02749.  , 2023
Link: http://arxiv.org/abs/230..
 
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