Xianlong Hong, Xianlong Hong
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1

Leakage power optimization for clock network using dual-Vth..:

, In: 2008 IEEE International Symposium on Circuits and Systems (ISCAS),
Weixiang Shen ; Yici Cai ; Xianlong Hong - p. None , 2008
 
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2

3D CBL: an efficient algorithm for general 3D packing probl..:

, In: 48th Midwest Symposium on Circuits and Systems, 2005.,
Yuchun Ma ; Xianlong Hong ; Sheqin Dong. - p. 1079-1082 Vol. 2 , 2005
 
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3

Congestion and performance driven full-chip scalable routin..:

, In: 2005 6th International Conference on ASIC,
Hailong Yao ; Yici Cai ; Xianlong Hong. - p. 856-859 , 2005
 
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10

A fast simulating algorithm for power/ground network with t..:

, In: ASIC, 2003. Proceedings. 5th International Conference on,
 
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11

Congestion based layer assignment of global routing:

, In: ASIC, 2003. Proceedings. 5th International Conference on,
 
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12

Reliable buffered clock tree routing algorithm with process..:

, In: ASIC, 2003. Proceedings. 5th International Conference on,
 
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15

Effective legitimate skew driven clock tree routing:

, In: ASIC, 2003. Proceedings. 5th International Conference on,
 
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