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2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ,
2
A Block Partitioning Method for Region Exhaustive Test to R..:
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2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ,
3
An Evaluation of Estimated Field Random Testability for Dat..:
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2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ,
4
An Evaluation of a Testability Measure for State Assignment..:
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2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ,
5
CRLock: A SAT and FALL Attacks Resistant Logic Locking Meth..:
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2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS) ,
6
A Low Capture Power Oriented X-Identification-Filling Co-Op..:
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2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ,
7
A Multiple Target Test Generation Method for Gate-Exhaustiv..:
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2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ,
8
A Low Capture Power Oriented X-filling Method Using Partial..:
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2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ,
9
A State Assignment Method to Improve Transition Fault Cover..:
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VLSI Design and Test for Systems Dependability ,
10
Malicious Attacks on Electronic Systems and VLSIs for Secur..:
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Proceedings of the 2001 Asia and South Pacific Design Automation Conference ,
15
Design for testability strategies using full/partial scan d..:
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