E-LIB Suche - Ergebnisse für: Yan, Jin-Tai

1

Design and analysis of sum-prediction adder:

Yen, Chia-Heng ; Yan, Jin-Tai
Integration. 96 (2024) - p. 102139 , 2024

Link: https://doi.org/10.1016/..

2

Layer-Minimization-Oriented GNR Area Routing:

, In: 2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS),

Yen, Chia-Heng ; Yan, Jin-Tai - p. 1-4 , 2023

Link: https://doi.org/10.1109/..

3

Ordered Escape Routing via Assignment of Routability-Driven..:

Yan, Jin-Tai
IEEE Transactions on Components, Packaging and Manufacturing Technology. 13 (2023) 4 - p. 451-464 , 2023

Link: https://doi.org/10.1109/..

4

Fuzzy-Based Balanced Partitioning Under Capacity and Size-T..:

Yan, Jin-Tai
IEEE Transactions on Quantum Engineering. 4 (2023) - p. 1-15 , 2023

Link: https://doi.org/10.1109/..

5

Bus-Aware IO Alignment Considering Length-Matching Constrai..:

Yan, Jin-Tai
IEEE Transactions on Components, Packaging and Manufacturing Technology. 13 (2023) 1 - p. 79-92 , 2023

Link: https://doi.org/10.1109/..

6

Bus Assignment Considering Flexible Escape Routing for Laye..:

Yan, Jin-Tai
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 41 (2022) 8 - p. 2699-2713 , 2022

Link: https://doi.org/10.1109/..

7

Single-Layer Obstacle-Aware Multiple-Bus Routing Considerin..:

Yan, Jin-Tai
IEEE Transactions on Components, Packaging and Manufacturing Technology. 12 (2022) 6 - p. 902-915 , 2022

Link: https://doi.org/10.1109/..

8

Fixed-Order Placement of Pipelined Architecture in Rapid Si..:

Yan, Jin-Tai
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 30 (2022) 10 - p. 1519-1532 , 2022

Link: https://doi.org/10.1109/..

9

Tree-Based Clock Distribution of Multiple-Stage Pipelined A..:

Yan, Jin-Tai
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 41 (2022) 4 - p. 1090-1102 , 2022

Link: https://doi.org/10.1109/..

10

Via-Avoidance-Oriented Interposer Routing for Layer Minimiz..:

Yan, Jin-Tai
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 29 (2021) 11 - p. 1889-1902 , 2021

Link: https://doi.org/10.1109/..

11

Via-Minimization-Oriented Region Routing Under Length-Match..:

Yan, Jin-Tai
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 29 (2021) 6 - p. 1257-1270 , 2021

Link: https://doi.org/10.1109/..

12

Single-Layer Obstacle-Aware Substrate Routing via Iterative..:

Yan, Jin-Tai
ACM Transactions on Design Automation of Electronic Systems (TODAES). 25 (2020) 2 - p. 1-21 , 2020

Link: https://dl.acm.org/doi/1..

13

Delay-Constrained GNR Routing for Layer Minimization:

Yan, Jin-Tai
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 28 (2020) 11 - p. 2356-2369 , 2020

Link: https://doi.org/10.1109/..

14

Single-Layer Obstacle-Aware Substrate Routing via Iterative..:

Yan, Jin-Tai
ACM Transactions on Design Automation of Electronic Systems. 25 (2020) 2 - p. 1-21 , 2020

Link: https://doi.org/10.1145/..

15

Single-Layer Delay-Driven GNR Nontree Routing Under Resourc..:

Yan, Jin-Tai
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 28 (2020) 3 - p. 736-749 , 2020

Link: https://doi.org/10.1109/..