I agree that this site is using cookies. You can find further informations here.
X
Yanagisawa, Masao
231  results:
Search for persons X
?
1

A Dual-Output Rectifier-Based Self-Powered Interface Circui..:

Su, Yirui ; Yanagisawa, Masao ; Shi, Youhua
IEEE Transactions on Power Electronics.  39 (2024)  6 - p. 6630-6634 , 2024
Link: https://doi.org/10.1109/..
 
?
2

An Area-Power-Efficient Multiplier-less Processing Element ..:

, In: 2023 IEEE 15th International Conference on ASIC (ASICON),
Li, Jiaxiang ; Yanagisawa, Masao ; Shi, Youhua - p. 1-4 , 2023
Link: https://doi.org/10.1109/..
 
?
3

Strategy for Improving Cycle of Maximized Energy Output of ..:

, In: 2023 International Conference on IC Design and Technology (ICICDT),
Su, Yirui ; Yanagisawa, Masao ; Shi, Youhua - p. 131-135 , 2023
Link: https://doi.org/10.1109/..
 
?
4

Scalable Hardware Efficient Architecture for Parallel FIR F..:

Ye, Jinghao ; Yanagisawa, Masao ; Shi, Youhua
Electronics.  11 (2022)  20 - p. 3272 , 2022
Link: https://doi.org/10.3390/..
 
?
5

Dataflow Optimization through Exploring Single-Layer and In..:

Ye, Jinghao ; Yanagisawa, Masao ; Shi, Youhua
Electronics.  11 (2022)  15 - p. 2356 , 2022
Link: https://doi.org/10.3390/..
 
?
6

Power-Efficient Deep Convolutional Neural Network Design Th..:

Ye, Lin ; Ye, Jinghao ; Yanagisawa, Masao.
IEEE Access.  9 (2021)  - p. 17411-17420 , 2021
Link: https://doi.org/10.1109/..
 
?
7

Faithfully Truncated Adder-Based Area-Power Efficient FIR D..:

YE, Jinghao ; YANAGISAWA, Masao ; SHI, Youhua
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences.  E103.A (2020)  9 - p. 1063-1070 , 2020
Link: https://doi.org/10.1587/..
 
?
8

A High-Performance Symmetric Hybrid Form Design for High-Or..:

, In: 2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS),
Ye, Jinghao ; Yanagisawa, Masao ; Shi, Youhua - p. 121-124 , 2020
Link: https://doi.org/10.1109/..
 
?
9

Trojan-Net Classification for Gate-Level Hardware Design Ut..:

HASEGAWA, Kento ; YANAGISAWA, Masao ; TOGAWA, Nozomu
IEICE Transactions on Information and Systems.  E103.D (2020)  7 - p. 1618-1622 , 2020
Link: https://doi.org/10.1587/..
 
?
10

Multi-Resolutional Image Format Using Stochastic Numbers an..:

, In: 2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS),
Ishikawa, Ryota ; Tawada, Masashi ; Yanagisawa, Masao. - p. 1-4 , 2020
Link: https://doi.org/10.1109/..
 
?
11

Scalable Stochastic Number Duplicators for Accuracy-flexibl..:

Ishikawa, Ryota ; Tawada, Masashi ; Yanagisawa, Masao.
IPSJ Transactions on System LSI Design Methodology.  13 (2020)  0 - p. 10-20 , 2020
Link: https://doi.org/10.2197/..
 
?
12

A Power-Efficient Soft Error Hardened Latch Design with In-..:

, In: 2019 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia),
Tajima, Saki ; Yanagisawa, Masao ; Shi, Youhua - p. 53-56 , 2019
Link: https://doi.org/10.1109/..
 
?
13

A Zero-Gating Processing Element Design for Low-Power Deep ..:

, In: 2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS),
Ye, Lin ; Ye, Jinghao ; Yanagisawa, Masao. - p. 317-320 , 2019
Link: https://doi.org/10.1109/..
 
?
14

Logistic regression analysis of multiple interosseous hand-..:

Yokoyama, Masayuki ; Yanagisawa, Masao
Journal of Electromyography and Kinesiology.  44 (2019)  - p. 117-123 , 2019
Link: https://doi.org/10.1016/..
 
?
15

A Multiple Cyclic-Route Generation Method with Route Length..:

NISHIMURA, Tensei ; ISHIKAWA, Kazuaki ; TAKAYAMA, Toshinori..
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences.  E102.A (2019)  4 - p. 641-653 , 2019
Link: https://doi.org/10.1587/..
 
1-15