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Yici Cai, Yici Cai
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1

Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis..:

Yici Cai ; Chao Deng ; Qiang Zhou...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  23 (2015)  1 - p. 142-155 , 2015
Link: https://doi.org/10.1109/..
 
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2

Leakage power optimization for clock network using dual-Vth..:

, In: 2008 IEEE International Symposium on Circuits and Systems (ISCAS),
Weixiang Shen ; Yici Cai ; Xianlong Hong - p. None , 2008
Link: https://doi.org/10.1109/..
 
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3

Congestion and performance driven full-chip scalable routin..:

, In: 2005 6th International Conference on ASIC,
Hailong Yao ; Yici Cai ; Xianlong Hong. - p. 856-859 , 2005
Link: https://doi.org/10.1109/..
 
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4

Standard-cell based data-path placement utilizing regularit:

, In: ASIC, 2003. Proceedings. 5th International Conference on,
Changqi Yang, Changqi Yang ; Xianlong Hong, Xianlong Hong ; Yici Cai, Yici Cai... - p. None , 2003
Link: https://doi.org/10.1109/..
 
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5

An O(nloglogn) algorithm for evaluation of Bounded Slice-li..:

, In: ASIC, 2003. Proceedings. 5th International Conference on,
Song Chen, Song Chen ; Xianlong Hong, Xianlong Hong ; Sheqin Dong, Sheqin Dong... - p. None , 2003
Link: https://doi.org/10.1109/..
 
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6

Reliable buffered clock tree routing algorithm with process..:

, In: ASIC, 2003. Proceedings. 5th International Conference on,
Yi Liu, Yi Liu ; Xianlong Hong, Xianlong Hong ; Yici Cai, Yici Cai. - p. None , 2003
Link: https://doi.org/10.1109/..
 
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7

Congestion based layer assignment of global routing:

, In: ASIC, 2003. Proceedings. 5th International Conference on,
Yi Zhou, Yi Zhou ; Qiang Zhou, Qiang Zhou ; Yici Cai, Yici Cai.. - p. None , 2003
Link: https://doi.org/10.1109/..
 
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8

A fast simulating algorithm for power/ground network with t..:

, In: ASIC, 2003. Proceedings. 5th International Conference on,
Jin Shi, Jin Shi ; Yici Cai, Yici Cai ; Zuying Luo, Zuying Luo. - p. None , 2003
Link: https://doi.org/10.1109/..
 
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9

Path-based timing optimization by buffer insertion with acc..:

, In: ASIC, 2003. Proceedings. 5th International Conference on,
Yiqian Zhang, Yiqian Zhang ; Qiang Zhou, Qiang Zhou ; Xianlong Hong, Xianlong Hong. - p. None , 2003
Link: https://doi.org/10.1109/..
 
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10

A multi-layer area routing algorithm with optimized pin map..:

, In: ASIC, 2003. Proceedings. 5th International Conference on,
Liu Yang, Liu Yang ; Xianlong Hong, Xianlong Hong ; Yici Cai, Yici Cai.. - p. None , 2003
Link: https://doi.org/10.1109/..
 
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11

Signal flow driven analog IC router:

, In: ASIC, 2003. Proceedings. 5th International Conference on,
Jun Liang, Jun Liang ; Changxu Du, Changxu Du ; Yici Cai, Yici Cai.. - p. None , 2003
Link: https://doi.org/10.1109/..
 
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12

Effective legitimate skew driven clock tree routing:

, In: ASIC, 2003. Proceedings. 5th International Conference on,
Meng Zhao, Meng Zhao ; Yici Cai, Yici Cai ; Xianlong Hong, Xianlong Hong.. - p. None , 2003
Link: https://doi.org/10.1109/..
 
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13

Decoupling capacitor allocation for power delivery network ..:

, In: ASIC, 2003. Proceedings. 5th International Conference on,
Jingjing Fu, Jingjing Fu ; Xianlong Hong, Xianlong Hong ; Yici Cai, Yici Cai. - p. None , 2003
Link: https://doi.org/10.1109/..
 
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14

Cross point assignment algorithm with crosstalk constraint:

, In: ASIC, 2003. Proceedings. 5th International Conference on,
Hailong Yao, Hailong Yao ; Qiang Zhou, Qiang Zhou ; Xianlong Hong, Xianlong Hong. - p. None , 2003
Link: https://doi.org/10.1109/..
 
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15

Area routing oriented hierarchical corner stitching with pa..:

, In: Proceedings of the 2000 Asia and South Pacific Design Automation Conference,
Yan, Zhang ; Baohua, Wang ; Yici, Cai. - p. 105-110 , 2000
Link: https://dl.acm.org/doi/1..
 
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