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Sequential logic testing and verification
Kluwer international series in engineering and computer science. SECS ; 163, VLSI, computer architecture and digital signal design
Ghosh, Abhijit
;
Devadas, Srinivas
, 1992
Exemplar:
Zentrale:E02
a inf 170 e/702
RT Book, Whole T1 <Title>Sequential logic testing and verification</Title> UL https://suche.suub.uni-bremen.de/peid=B01968154&Exemplar=1&LAN=DE A1 Ghosh, Abhijit A1 Devadas, Srinivas PB Kluwer Academic Publishers PP Boston [u.a.] YR 1992 NO XV, 214 S : graph. Darst T3 Kluwer international series in engineering and computer science. SECS ; 163, VLSI, computer architecture and digital signal design SN 0792391888 SN 9780792391883 VO 163 : VLSI, computer architecture and digital signal processing LK http://katalog.suub.uni-bremen.de/DB=1/LNG=DU/CMD?ACT=SRCHA&IKT=8000&TRM=16586568* CN E02: a inf 170 e/702 SF ELIB - SuUB Bremen
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