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High level synthesis of ASICs under timing and synchronizat..
The Kluwer international series in engineering and computer science ; 177, VLSI, computer architecture and digital signal processing
Ku, David C.
, 1992
Exemplar:
Zentrale:E02
a inf 110 hdl/692
RT Book, Whole T1
High level synthesis of ASICs under timing and synchronization constraints
UL https://suche.suub.uni-bremen.de/peid=B162123761&Exemplar=1&LAN=DE A1 Ku, David C. PB Kluwer Acad. Publ. PP Boston [u.a.] YR 1992 NO XIII, 294 S. ; 25 cm : graph. Darst. T3 The Kluwer international series in engineering and computer science ; 177, VLSI, computer architecture and digital signal processing SN 0792392442 SN 9780792392446 VO 177 LK http://katalog.suub.uni-bremen.de/DB=1/LNG=DU/CMD?ACT=SRCHA&IKT=8000&TRM=1610878701* CN E02: a inf 110 hdl/692 SF ELIB - SuUB Bremen
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