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1 Ergebnisse
1
Layout-Aware Scan Chain Synthesis for Improved Path Delay F..:
, In:
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
,
Gupta, Puneet
;
Kahng, Andrew B.
;
Mandoiu, Ion
. - p. 754 ff. , 2003
Link:
https://dl.acm.org/doi/10.5555/996070.1009972
RT T1
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
: T1
Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage
UL https://suche.suub.uni-bremen.de/peid=acm-1009972&Exemplar=1&LAN=DE A1 Gupta, Puneet A1 Kahng, Andrew B. A1 Mandoiu, Ion A1 Sharma, Puneet PB IEEE Computer Society YR 2003 K1 Hardware K1 Robustness K1 Hardware test K1 Electronic design automation K1 Physical design (EDA) K1 Wire routing K1 Partitioning and floorplanning K1 Placement SP 754 ff. LK http://dx.doi.org/https://dl.acm.org/doi/10.5555/996070.1009972 DO https://dl.acm.org/doi/10.5555/996070.1009972 SF ELIB - SuUB Bremen
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