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An efficient system-on-a-chip design methodology for networ..:
, In:
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
,
Salapura, Valentina
;
Georgiou, Christos J.
;
Nair, Indira
- p. 212-219 , 2004
Link:
https://dl.acm.org/doi/10.1145/1023833.1023863
RT T1 <cTitle>Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems</cTitle>: T1 <Title>An efficient system-on-a-chip design methodology for networking applications</Title> UL https://suche.suub.uni-bremen.de/peid=acm-1023863&Exemplar=1&LAN=DE A1 Salapura, Valentina A1 Georgiou, Christos J. A1 Nair, Indira PB ACM YR 2004 K1 network processor K1 system-on-a-chip K1 Computer systems organization K1 Embedded and cyber-physical systems K1 Real-time systems K1 Applied computing K1 Computers in other domains K1 Personal computers and PC applications K1 Microcomputers K1 Hardware K1 Very large scale integration design K1 VLSI system specification and constraints K1 Architectures K1 Parallel architectures SP 212 OP 219 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/1023833.1023863 DO https://dl.acm.org/doi/10.1145/1023833.1023863 SF ELIB - SuUB Bremen
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