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1 Ergebnisse
1
Simulation Methodology for Analysis of Substrate Noise Impa..:
, In:
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
,
Soens, C.
;
Plas, G. Van der
;
Wambacq, P.
. - p. 270-275 , 2005
Link:
https://dl.acm.org/doi/10.1109/DATE.2005.268
RT T1
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
: T1
Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance
UL https://suche.suub.uni-bremen.de/peid=acm-1049113&Exemplar=1&LAN=DE A1 Soens, C. A1 Plas, G. Van der A1 Wambacq, P. A1 Donnay, S. PB IEEE Computer Society YR 2005 K1 Hardware K1 Hardware validation K1 Functional verification K1 Simulation and emulation K1 Communication hardware, interfaces and storage K1 Buses and high-speed links K1 Computing methodologies K1 Modeling and simulation K1 Model development and analysis K1 Modeling methodologies SP 270 OP 275 LK http://dx.doi.org/https://dl.acm.org/doi/10.1109/DATE.2005.268 DO https://dl.acm.org/doi/10.1109/DATE.2005.268 SF ELIB - SuUB Bremen
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