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1 Ergebnisse
1
Store Buffer Design in First-Level Multibanked Data Caches:
, In:
Proceedings of the 32nd annual international symposium on Computer Architecture
,
Torres, E. F.
;
Ibanez, P.
;
Vinals, V.
. - p. 469-480 , 2005
Link:
https://dl.acm.org/doi/10.1109/ISCA.2005.47
RT T1 <cTitle>Proceedings of the 32nd annual international symposium on Computer Architecture</cTitle>: T1 <Title>Store Buffer Design in First-Level Multibanked Data Caches</Title> UL https://suche.suub.uni-bremen.de/peid=acm-1070009&Exemplar=1&LAN=DE A1 Torres, E. F. A1 Ibanez, P. A1 Vinals, V. A1 Llaberia, J. M. PB IEEE Computer Society YR 2005 K1 Hardware K1 Electronic design automation K1 High-level and register-transfer level synthesis K1 Integrated circuits K1 Semiconductor memory K1 Datapath optimization K1 Hardware validation K1 Functional verification K1 Simulation and emulation K1 Very large scale integration design K1 VLSI packaging K1 Input / output styles K1 Application-specific VLSI designs K1 Application specific processors SP 469 OP 480 LK http://dx.doi.org/https://dl.acm.org/doi/10.1109/ISCA.2005.47 DO https://dl.acm.org/doi/10.1109/ISCA.2005.47 SF ELIB - SuUB Bremen
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