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Exploring the cache design space for large scale CMPs:
Hsu, Lisa
;
Iyer, Ravi
;
Makineni, Srihari
..
ACM SIGARCH Computer Architecture News. 33 (2005) 4 - p. 24-33 , 2005
Link:
https://dl.acm.org/doi/10.1145/1105734.1105739
RT Journal T1 <Title>Exploring the cache design space for large scale CMPs</Title> UL https://suche.suub.uni-bremen.de/peid=acm-1105739&Exemplar=1&LAN=DE A1 Hsu, Lisa A1 Iyer, Ravi A1 Makineni, Srihari A1 Reinhardt, Steve A1 Newell, Donald PB ACM YR 2005 SN 0163-5964 K1 Hardware K1 Integrated circuits K1 Semiconductor memory K1 Dynamic memory K1 Computer systems organization K1 Architectures K1 Parallel architectures K1 Multiple instruction, multiple data K1 Dependable and fault-tolerant systems and networks K1 Networks K1 Network performance evaluation K1 General and reference K1 Cross-computing tools and techniques K1 Performance JF ACM SIGARCH Computer Architecture News VO 33 IS 4 SP 24 OP 33 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/1105734.1105739 DO https://dl.acm.org/doi/10.1145/1105734.1105739 SF ELIB - SuUB Bremen
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