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Constraint driven I/O planning and placement for chip-packa..:

, In: Proceedings of the 2006 Asia and South Pacific Design Automation Conference,

Xiong, Jinjun ; Wong, Yiu-Chung ; Sarto, Egino. - p. 207-212 , 2006

Link: https://dl.acm.org/doi/10.1145/1118299.1118356

RT 
T1 <cTitle>Proceedings of the 2006 Asia and South Pacific Design Automation Conference</cTitle>: T1 <Title>Constraint driven I/O planning and placement for chip-package co-design</Title>

UL https://suche.suub.uni-bremen.de/peid=acm-1118356&Exemplar=1&LAN=DE
				
A1 Xiong, Jinjun
A1 Wong, Yiu-Chung
A1 Sarto, Egino
A1 He, Lei
PB IEEE Press
YR 2006
K1 Hardware
K1 Electronic design automation
K1 Physical design (EDA)
K1 Wire routing
K1 Placement
K1 Mathematics of computing
K1 Mathematical analysis
K1 Mathematical optimization
K1 Mixed discrete-continuous optimization
K1 Integer programming
K1 Logic synthesis
K1 Circuit optimization
K1 Applied computing
K1 Physical sciences and engineering
K1 Mathematics and statistics
K1 Numerical analysis
K1 Integrated circuits
K1 Interconnect
K1 Input / output circuits
K1 Continuous optimization
K1 Linear programming
K1 Theory of computation
K1 Design and analysis of algorithms
SP 207
OP 212
LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/1118299.1118356
DO https://dl.acm.org/doi/10.1145/1118299.1118356
SF ELIB - SuUB Bremen

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