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Diagonal routing in high performance microprocessor design:

, In: Proceedings of the 2006 Asia and South Pacific Design Automation Conference,

Ito, Noriyuki ; Katagiri, Hideaki ; Yamashita, Ryoichi... - p. 624-629 , 2006

Link: https://dl.acm.org/doi/10.1145/1118299.1118446

RT 
T1 <cTitle>Proceedings of the 2006 Asia and South Pacific Design Automation Conference</cTitle>: T1 <Title>Diagonal routing in high performance microprocessor design</Title>

UL https://suche.suub.uni-bremen.de/peid=acm-1118446&Exemplar=1&LAN=DE
				
A1 Ito, Noriyuki
A1 Katagiri, Hideaki
A1 Yamashita, Ryoichi
A1 Ikeda, Hiroshi
A1 Sugiyama, Hiroyuki
A1 Komatsu, Hiroaki
A1 Tanamura, Yoshiyasu
A1 Yoshitake, Akihiko
A1 Nonomura, Kazuhiro
A1 Ishizaka, Kinya
A1 Adachi, Hiroaki
A1 Mori, Yutaka
A1 Isoda, Yutaka
A1 Sugiyama, Yaroku
PB IEEE Press
YR 2006
K1 diagonal routing
K1 manhattan routing
K1 microprocessor
K1 Hardware
K1 Electronic design automation
K1 Physical design (EDA)
K1 Placement
K1 Wire routing
K1 Hardware validation
K1 Integrated circuits
K1 Theory of computation
K1 Design and analysis of algorithms
K1 Approximation algorithms analysis
K1 Routing and network design problems
SP 624
OP 629
LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/1118299.1118446
DO https://dl.acm.org/doi/10.1145/1118299.1118446
SF ELIB - SuUB Bremen

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