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A fractional delay-locked loop for on chip clock generation..:

, In: Proceedings of the 2005 Asia and South Pacific Design Automation Conference,
Torkzadeh, P. ; Tajalli, A. ; Atarodi, M. - p. 1300-1309 , 2005
Link: https://dl.acm.org/doi/10.1145/1120725.1121048