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1 Ergebnisse
1
Sensing Margin Analysis of MLC Flash Memories Using a Novel..:
, In:
Proceedings of the 7th International Symposium on Quality Electronic Design
,
Kim, Young-Gu
;
Lee, Sang-Hoon
;
Kim, Dae-Han
... - p. 185-189 , 2006
Link:
https://dl.acm.org/doi/10.1109/ISQED.2006.113
RT T1 <cTitle>Proceedings of the 7th International Symposium on Quality Electronic Design</cTitle>: T1 <Title>Sensing Margin Analysis of MLC Flash Memories Using a Novel Unified Statistical Model</Title> UL https://suche.suub.uni-bremen.de/peid=acm-1126749&Exemplar=1&LAN=DE A1 Kim, Young-Gu A1 Lee, Sang-Hoon A1 Kim, Dae-Han A1 Im, Jae-Woo A1 Yu, Sung-Eun A1 Kim, Dae-Wook A1 Park, Young-Kwan A1 Kong, Jeong-Taek PB IEEE Computer Society YR 2006 K1 Hardware K1 Electronic design automation K1 Logic synthesis K1 Circuit optimization K1 Integrated circuits K1 Logic circuits K1 Finite state machines K1 Semiconductor memory K1 Hardware validation SP 185 OP 189 LK http://dx.doi.org/https://dl.acm.org/doi/10.1109/ISQED.2006.113 DO https://dl.acm.org/doi/10.1109/ISQED.2006.113 SF ELIB - SuUB Bremen
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