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A two-port SRAM for real-time video processor saving 53% of..:
, In:
Proceedings of the 2006 international symposium on Low power electronics and design
,
Fujiwara, Hidehiro
;
Nii, Koji
;
Miyakoshi, Junichi
... - p. 61-66 , 2006
Link:
https://dl.acm.org/doi/10.1145/1165573.1165589
RT T1 <cTitle>Proceedings of the 2006 international symposium on Low power electronics and design</cTitle>: T1 <Title>A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering</Title> UL https://suche.suub.uni-bremen.de/peid=acm-1165589&Exemplar=1&LAN=DE A1 Fujiwara, Hidehiro A1 Nii, Koji A1 Miyakoshi, Junichi A1 Murachi, Yuichiro A1 Morita, Yasuhiro A1 Kawaguchi, Hiroshi A1 Yoshimoto, Masahiko PB ACM YR 2006 K1 data-bit reordering K1 low power SRAM K1 majority logic K1 real-time image processing K1 two-port SRAM K1 Hardware K1 Integrated circuits K1 Semiconductor memory K1 Static memory SP 61 OP 66 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/1165573.1165589 DO https://dl.acm.org/doi/10.1145/1165573.1165589 SF ELIB - SuUB Bremen
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