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System-level power-performance trade-offs in bus matrix com..:
, In:
Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
,
Pasricha, Sudeep
;
Park, Young-Hwan
;
Kurdahi, Fadi J.
. - p. 300-305 , 2006
Link:
https://dl.acm.org/doi/10.1145/1176254.1176327
RT T1 <cTitle>Proceedings of the 4th international conference on Hardware/software codesign and system synthesis</cTitle>: T1 <Title>System-level power-performance trade-offs in bus matrix communication architecture synthesis</Title> UL https://suche.suub.uni-bremen.de/peid=acm-1176327&Exemplar=1&LAN=DE A1 Pasricha, Sudeep A1 Park, Young-Hwan A1 Kurdahi, Fadi J. A1 Dutt, Nikil PB ACM YR 2006 K1 bus matrix synthesis K1 communication architectures K1 power estimation K1 power-performance trade-offs K1 system-on-chip K1 Applied computing K1 Arts and humanities K1 Architecture (buildings) K1 Computer-aided design K1 Physical sciences and engineering K1 Engineering K1 Hardware K1 Very large scale integration design K1 VLSI system specification and constraints K1 Electronic design automation K1 Physical design (EDA) SP 300 OP 305 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/1176254.1176327 DO https://dl.acm.org/doi/10.1145/1176254.1176327 SF ELIB - SuUB Bremen
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