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1 Ergebnisse
1
High-level power analysis for multi-core chips:
, In:
Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
,
Eisley, Noel
;
Soteriou, Vassos
;
Peh, Li-Shiuan
- p. 389-400 , 2006
Link:
https://dl.acm.org/doi/10.1145/1176760.1176807
RT T1
Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
: T1
High-level power analysis for multi-core chips
UL https://suche.suub.uni-bremen.de/peid=acm-1176807&Exemplar=1&LAN=DE A1 Eisley, Noel A1 Soteriou, Vassos A1 Peh, Li-Shiuan PB ACM YR 2006 K1 chip multiprocessor (CMP) K1 multi-core K1 power analysis K1 simulation K1 system-on-a-chip (SoC) K1 Hardware K1 Hardware validation K1 Communication hardware, interfaces and storage K1 Networks SP 389 OP 400 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/1176760.1176807 DO https://dl.acm.org/doi/10.1145/1176760.1176807 SF ELIB - SuUB Bremen
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