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1 Ergebnisse
1
Selective code transformation for dual instruction set proc..:
Lee, Sheayun
;
Lee, Jaejin
;
Park, Chang Yun
.
ACM Transactions on Embedded Computing Systems (TECS). 6 (2007) 2 - p. 10-es , 2007
Link:
https://dl.acm.org/doi/10.1145/1234675.1234677
RT Journal T1
Selective code transformation for dual instruction set processors
UL https://suche.suub.uni-bremen.de/peid=acm-1234677&Exemplar=1&LAN=DE A1 Lee, Sheayun A1 Lee, Jaejin A1 Park, Chang Yun A1 Min, Sang Lyul PB ACM YR 2007 SN 1539-9087 SN 1558-3465 K1 Dual instruction set processors K1 mixed-width instruction set architecture K1 reduced bid-width instruction set architecture JF ACM Transactions on Embedded Computing Systems (TECS) VO 6 IS 2 SP 10 OP es LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/1234675.1234677 DO https://dl.acm.org/doi/10.1145/1234675.1234677 SF ELIB - SuUB Bremen
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