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1 Ergebnisse
1
Timing- and constraint-oriented placement for interconnecte..:
, In:
Proceedings of the 28th ACM/IEEE Design Automation Conference
,
Ogawa, Yasushi
;
Itoh, Tsutomu
;
Miki, Yoshio
... - p. 253-258 , 1991
Link:
https://dl.acm.org/doi/10.1145/127601.127676
RT T1 <cTitle>Proceedings of the 28th ACM/IEEE Design Automation Conference</cTitle>: T1 <Title>Timing- and constraint-oriented placement for interconnected LSIs in mainframe design</Title> UL https://suche.suub.uni-bremen.de/peid=acm-127676&Exemplar=1&LAN=DE A1 Ogawa, Yasushi A1 Itoh, Tsutomu A1 Miki, Yoshio A1 Ishii, Tatsuki A1 Sato, Yasuo A1 Toyoshima, Reiji PB ACM YR 1991 K1 Hardware K1 Electronic design automation K1 Physical design (EDA) K1 Partitioning and floorplanning K1 Integrated circuits K1 Interconnect K1 Logic synthesis K1 Circuit optimization K1 Computer systems organization K1 Architectures K1 Very large scale integration design K1 Application-specific VLSI designs SP 253 OP 258 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/127601.127676 DO https://dl.acm.org/doi/10.1145/127601.127676 SF ELIB - SuUB Bremen
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