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Vt balancing and device sizing towards high yield of sub-th..:

, In: Proceedings of the 2007 international symposium on Low power electronics and design,
Pu, Yu ; de Gyvez, Jose de jesus Pineda ; Corporaal, Henk. - p. 355-358 , 2007
Link: https://dl.acm.org/doi/10.1145/1283780.1283857