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Phase-based cache reconfiguration for a highly-configurable..:
, In:
Proceedings of the 18th ACM Great Lakes symposium on VLSI
,
Gordon-Ross, Ann
;
Lau, Jeremy
;
Calder, Brad
- p. 379-382 , 2008
Link:
https://dl.acm.org/doi/10.1145/1366110.1366200
RT T1
Proceedings of the 18th ACM Great Lakes symposium on VLSI
: T1
Phase-based cache reconfiguration for a highly-configurable two-level cache hierarchy
UL https://suche.suub.uni-bremen.de/peid=acm-1366200&Exemplar=1&LAN=DE A1 Gordon-Ross, Ann A1 Lau, Jeremy A1 Calder, Brad PB ACM YR 2008 K1 cache tuning K1 caches K1 configurable architecture K1 configurable caches K1 phase prediction K1 phase-based reconfiguration K1 phase-based tuning K1 Hardware K1 Integrated circuits K1 Semiconductor memory K1 Dynamic memory SP 379 OP 382 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/1366110.1366200 DO https://dl.acm.org/doi/10.1145/1366110.1366200 SF ELIB - SuUB Bremen
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