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An elementary processor architecture with simultaneous inst..:

, In: Proceedings of the 19th annual international symposium on Computer architecture,

Hirata, Hiroaki ; Kimura, Kozo ; Nagamine, Satoshi... - p. 136-145 , 1992

Link: https://dl.acm.org/doi/10.1145/139669.139710

RT 
T1 <cTitle>Proceedings of the 19th annual international symposium on Computer architecture</cTitle>: T1 <Title>An elementary processor architecture with simultaneous instruction issuing from multiple threads</Title>

UL https://suche.suub.uni-bremen.de/peid=acm-139710&Exemplar=1&LAN=DE
				
A1 Hirata, Hiroaki
A1 Kimura, Kozo
A1 Nagamine, Satoshi
A1 Mochizuki, Yoshiyuki
A1 Nishimura, Akio
A1 Nakase, Yoshimori
A1 Nishizawa, Teiji
PB ACM
YR 1992
K1 Computer systems organization
K1 Architectures
K1 Serial architectures
K1 Complex instruction set computing
K1 Reduced instruction set computing
K1 Parallel architectures
K1 Very long instruction word
K1 Dependable and fault-tolerant systems and networks
K1 General and reference
K1 Cross-computing tools and techniques
K1 Performance
K1 Networks
K1 Network performance evaluation
K1 Multiple instruction, multiple data
K1 Software and its engineering
K1 Software organization and properties
K1 Contextual software domains
K1 Operating systems
K1 Process management
K1 Scheduling
SP 136
OP 145
LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/139669.139710
DO https://dl.acm.org/doi/10.1145/139669.139710
SF ELIB - SuUB Bremen

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