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1 Ergebnisse
1
A simplified executable model to evaluate latency and throu..:
, In:
Proceedings of the 21st annual symposium on Integrated circuits and system design
,
Ost, Luciano
;
Moraes, Fernando G.
;
Möller, Leandro
... - p. 170-175 , 2008
Link:
https://dl.acm.org/doi/10.1145/1404371.1404420
RT T1
Proceedings of the 21st annual symposium on Integrated circuits and system design
: T1
A simplified executable model to evaluate latency and throughput of networks-on-chip
UL https://suche.suub.uni-bremen.de/peid=acm-1404420&Exemplar=1&LAN=DE A1 Ost, Luciano A1 Moraes, Fernando G. A1 Möller, Leandro A1 Indrusiak, Leandro Soares A1 Glesner, Manfred A1 Määttä, Sanna A1 Nurmi, Jari PB ACM YR 2008 K1 modeling K1 networks-on-chip K1 performance evaluation K1 Hardware K1 Emerging technologies K1 Very large scale integration design SP 170 OP 175 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/1404371.1404420 DO https://dl.acm.org/doi/10.1145/1404371.1404420 SF ELIB - SuUB Bremen
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