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Code scheduling for VLIW/superscalar processors with limite..:

, In: Proceedings of the 25th annual international symposium on Microarchitecture,

Kiyohara, Tokuzo ; Gyllenhaal, John C. - p. 197-201 , 1992

Link: https://dl.acm.org/doi/10.5555/144953.145802

RT 
T1 <cTitle>Proceedings of the 25th annual international symposium on Microarchitecture</cTitle>: T1 <Title>Code scheduling for VLIW/superscalar processors with limited register files</Title>

UL https://suche.suub.uni-bremen.de/peid=acm-145802&Exemplar=1&LAN=DE
				
A1 Kiyohara, Tokuzo
A1 Gyllenhaal, John C.
PB IEEE Computer Society Press
YR 1992
K1 Hardware
K1 Electronic design automation
K1 High-level and register-transfer level synthesis
K1 Very large scale integration design
K1 Application-specific VLSI designs
K1 Application specific instruction set processors
K1 Theory of computation
K1 Theory and algorithms for application domains
K1 Machine learning theory
K1 Reinforcement learning
K1 Sequential decision making
K1 Design and analysis of algorithms
K1 Approximation algorithms analysis
K1 Scheduling algorithms
K1 Online algorithms
K1 Online learning algorithms
SP 197
OP 201
LK http://dx.doi.org/https://dl.acm.org/doi/10.5555/144953.145802
DO https://dl.acm.org/doi/10.5555/144953.145802
SF ELIB - SuUB Bremen

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