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A methodology for tuning two-level cache hierarchy consider..:
, In:
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
,
Silva-Filho, A. G.
;
Araújo, C. C.
- p. 1-6 , 2009
Link:
https://dl.acm.org/doi/10.1145/1601896.1601905
RT T1
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
: T1
A methodology for tuning two-level cache hierarchy considering energy and performance
UL https://suche.suub.uni-bremen.de/peid=acm-1601905&Exemplar=1&LAN=DE A1 Silva-Filho, A. G. A1 Araújo, C. C. PB ACM YR 2009 K1 embedded systems K1 exploration mechanism K1 low power design K1 memory hierarchy K1 system-on-chip K1 two-level caches K1 Hardware K1 Integrated circuits K1 Semiconductor memory K1 Dynamic memory SP 1 OP 6 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/1601896.1601905 DO https://dl.acm.org/doi/10.1145/1601896.1601905 SF ELIB - SuUB Bremen
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