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1
Architecture for dense matrix multiplication on a high-perf..:
, In:
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
,
de Souza, Viviane L. S.
;
de Medeiros, Victor W. C.
;
de Lima, Manoel E.
- p. 1-6 , 2009
Link:
https://dl.acm.org/doi/10.1145/1601896.1601950
RT T1
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
: T1
Architecture for dense matrix multiplication on a high-performance reconfigurable system
UL https://suche.suub.uni-bremen.de/peid=acm-1601950&Exemplar=1&LAN=DE A1 de Souza, Viviane L. S. A1 de Medeiros, Victor W. C. A1 de Lima, Manoel E. PB ACM YR 2009 K1 BRAMs (RAM blocks) K1 FPGA (field programmable gate array) K1 MAC (multiplier unit) K1 RASC (reconfigurable application-specific computing) K1 data reuse K1 matrix multiplication K1 parallelism K1 performance K1 Hardware K1 Integrated circuits K1 Logic circuits K1 Arithmetic and datapath circuits K1 Theory of computation K1 Design and analysis of algorithms K1 Parallel algorithms K1 Computing methodologies K1 Parallel computing methodologies SP 1 OP 6 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/1601896.1601950 DO https://dl.acm.org/doi/10.1145/1601896.1601950 SF ELIB - SuUB Bremen
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