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1 Ergebnisse
1
TIM : a timing package for two-phase, level-clocked circ..:
, In:
Proceedings of the 30th international Design Automation Conference
,
Papaefthymiou, Marios C.
;
Randall, Keith H.
- p. 497-502 , 1993
Link:
https://dl.acm.org/doi/10.1145/157485.164998
RT T1
Proceedings of the 30th international Design Automation Conference
: T1
TIM : a timing package for two-phase, level-clocked circuitry
UL https://suche.suub.uni-bremen.de/peid=acm-164998&Exemplar=1&LAN=DE A1 Papaefthymiou, Marios C. A1 Randall, Keith H. PB ACM YR 1993 K1 Hardware K1 Integrated circuits K1 Logic circuits K1 Sequential circuits K1 Combinational circuits K1 Electronic design automation K1 Logic synthesis K1 Circuit optimization K1 Mathematics of computing K1 Discrete mathematics K1 Graph theory K1 Graph algorithms K1 Hardware validation K1 Functional verification SP 497 OP 502 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/157485.164998 DO https://dl.acm.org/doi/10.1145/157485.164998 SF ELIB - SuUB Bremen
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