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An hybrid eDRAM/SRAM macrocell to implement first-level dat..:
, In:
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
,
Valero, Alejandro
;
Sahuquillo, Julio
;
Petit, Salvador
... - p. 213-221 , 2009
Link:
https://dl.acm.org/doi/10.1145/1669112.1669140
RT T1 <cTitle>Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture</cTitle>: T1 <Title>An hybrid eDRAM/SRAM macrocell to implement first-level data caches</Title> UL https://suche.suub.uni-bremen.de/peid=acm-1669140&Exemplar=1&LAN=DE A1 Valero, Alejandro A1 Sahuquillo, Julio A1 Petit, Salvador A1 Lorente, Vicente A1 Canal, Ramon A1 López, Pedro A1 Duato, José PB ACM YR 2009 K1 leakage current K1 retention time K1 static and dynamic memory cells K1 Hardware K1 Integrated circuits K1 Semiconductor memory SP 213 OP 221 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/1669112.1669140 DO https://dl.acm.org/doi/10.1145/1669112.1669140 SF ELIB - SuUB Bremen
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