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1
Optimizing shared cache behavior of chip multiprocessors:
, In:
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
,
Kandemir, Mahmut
;
Muralidhara, Sai Prashanth
;
Narayanan, Sri Hari Krishna
.. - p. 505-516 , 2009
Link:
https://dl.acm.org/doi/10.1145/1669112.1669176
RT T1 <cTitle>Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture</cTitle>: T1 <Title>Optimizing shared cache behavior of chip multiprocessors</Title> UL https://suche.suub.uni-bremen.de/peid=acm-1669176&Exemplar=1&LAN=DE A1 Kandemir, Mahmut A1 Muralidhara, Sai Prashanth A1 Narayanan, Sri Hari Krishna A1 Zhang, Yuanrui A1 Ozturk, Ozcan PB ACM YR 2009 K1 Software and its engineering K1 Software notations and tools K1 Compilers K1 Hardware K1 Integrated circuits K1 Semiconductor memory K1 Dynamic memory SP 505 OP 516 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/1669112.1669176 DO https://dl.acm.org/doi/10.1145/1669112.1669176 SF ELIB - SuUB Bremen
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