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A parallel preconditioning strategy for efficient transisto..:

, In: Proceedings of the 2009 International Conference on Computer-Aided Design,

Thornquist, Heidi K. ; Keiter, Eric R. ; Hoekstra, Robert J... - p. 410-417 , 2009

Link: https://dl.acm.org/doi/10.1145/1687399.1687477

RT 
T1 <cTitle>Proceedings of the 2009 International Conference on Computer-Aided Design</cTitle>: T1 <Title>A parallel preconditioning strategy for efficient transistor-level circuit simulation</Title>

UL https://suche.suub.uni-bremen.de/peid=acm-1687477&Exemplar=1&LAN=DE
				
A1 Thornquist, Heidi K.
A1 Keiter, Eric R.
A1 Hoekstra, Robert J.
A1 Day, David M.
A1 Boman, Erik G.
PB ACM
YR 2009
K1 circuit simulation
K1 hypergraph partitioning
K1 iterative matrix solvers
K1 multi-core
K1 parallel simulation
K1 preconditioners
K1 Applied computing
K1 Physical sciences and engineering
K1 Engineering
K1 Mathematics of computing
K1 Mathematical analysis
K1 Numerical analysis
K1 Computations on matrices
K1 Computing methodologies
K1 Symbolic and algebraic manipulation
K1 Symbolic and algebraic algorithms
K1 Linear algebra algorithms
K1 Mathematical software
SP 410
OP 417
LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/1687399.1687477
DO https://dl.acm.org/doi/10.1145/1687399.1687477
SF ELIB - SuUB Bremen

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