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Logic synthesis for low power using clock gating and rewiri..:

, In: Proceedings of the 20th symposium on Great lakes symposium on VLSI,
Lam, Tak-Kei ; Yang, Steve ; Tang, Wai-Chung. - p. 179-184 , 2010
Link: https://dl.acm.org/doi/10.1145/1785481.1785527