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1 Ergebnisse
1
Characteristics of MS-CMOS logic in sub-32nm technologies:
, In:
Proceedings of the 20th symposium on Great lakes symposium on VLSI
,
Irez, Kagan
;
Hu, Jiaping
;
Zukowski, Charles A.
- p. 393-396 , 2010
Link:
https://dl.acm.org/doi/10.1145/1785481.1785572
RT T1
Proceedings of the 20th symposium on Great lakes symposium on VLSI
: T1
Characteristics of MS-CMOS logic in sub-32nm technologies
UL https://suche.suub.uni-bremen.de/peid=acm-1785572&Exemplar=1&LAN=DE A1 Irez, Kagan A1 Hu, Jiaping A1 Zukowski, Charles A. PB ACM YR 2010 K1 MSCMOS K1 domino K1 downsizing K1 gate leakage reduction K1 hs&ls K1 input vector K1 logic overhead K1 noise margin K1 upsizing K1 Hardware K1 Very large scale integration design SP 393 OP 396 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/1785481.1785572 DO https://dl.acm.org/doi/10.1145/1785481.1785572 SF ELIB - SuUB Bremen
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