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1 Ergebnisse
1
Process-induced skew variation for scaled 2-D and 3-D ICs:
, In:
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
,
Xu, Hu
;
Pavlidis, Vasilis F.
;
De Micheli, Giovanni
- p. 17-24 , 2010
Link:
https://dl.acm.org/doi/10.1145/1811100.1811107
RT T1
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
: T1
Process-induced skew variation for scaled 2-D and 3-D ICs
UL https://suche.suub.uni-bremen.de/peid=acm-1811107&Exemplar=1&LAN=DE A1 Xu, Hu A1 Pavlidis, Vasilis F. A1 De Micheli, Giovanni PB ACM YR 2010 K1 3-d ics K1 clock distribution networks K1 clock skew K1 process variations K1 technology scaling K1 Hardware K1 Very large scale integration design SP 17 OP 24 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/1811100.1811107 DO https://dl.acm.org/doi/10.1145/1811100.1811107 SF ELIB - SuUB Bremen
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