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Minimizing clock latency range in robust clock tree synthes..:

, In: Proceedings of the 2010 Asia and South Pacific Design Automation Conference,
Liu, Wen-Hao ; Li, Yih-Lang ; Chen, Hui-Chi - p. 389-394 , 2010
Link: https://dl.acm.org/doi/10.5555/1899721.1899817