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A New Algorithm for VHDL Parallel Simulation:
García-Dopico, Antonio
;
Pérez, Antonio
;
Rodríguez, Santiago
.
ACM Transactions on Design Automation of Electronic Systems (TODAES). 16 (2011) 3 - p. 1-31 , 2011
Link:
https://dl.acm.org/doi/10.1145/1970353.1970360
RT Journal T1
A New Algorithm for VHDL Parallel Simulation
UL https://suche.suub.uni-bremen.de/peid=acm-1970360&Exemplar=1&LAN=DE A1 García-Dopico, Antonio A1 Pérez, Antonio A1 Rodríguez, Santiago A1 García, María Isabel PB ACM YR 2011 SN 1084-4309 SN 1557-7309 K1 VHDL K1 parallel K1 simulation K1 Hardware K1 Hardware validation K1 Functional verification K1 Simulation and emulation K1 Electronic design automation K1 Hardware description languages and compilation K1 Computing methodologies K1 Parallel computing methodologies K1 Parallel programming languages K1 Software and its engineering K1 Software notations and tools K1 General programming languages K1 Language types K1 Modeling and simulation K1 Simulation types and techniques K1 Massively parallel and high-performance simulations K1 Discrete-event simulation JF ACM Transactions on Design Automation of Electronic Systems (TODAES) VO 16 IS 3 SP 1 OP 31 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/1970353.1970360 DO https://dl.acm.org/doi/10.1145/1970353.1970360 SF ELIB - SuUB Bremen
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