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1
Buffering of frequent accesses for reduced cache aging:
, In:
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
,
Calimera, Andrea
;
Loghi, Mirko
;
Macii, Enrico
. - p. 295-300 , 2011
Link:
https://dl.acm.org/doi/10.1145/1973009.1973068
RT T1
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
: T1
Buffering of frequent accesses for reduced cache aging
UL https://suche.suub.uni-bremen.de/peid=acm-1973068&Exemplar=1&LAN=DE A1 Calimera, Andrea A1 Loghi, Mirko A1 Macii, Enrico A1 Poncino, Massimo PB ACM YR 2011 K1 aging K1 leakage reduction K1 memory hierarchy K1 Hardware K1 Integrated circuits K1 Semiconductor memory K1 Dynamic memory SP 295 OP 300 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/1973009.1973068 DO https://dl.acm.org/doi/10.1145/1973009.1973068 SF ELIB - SuUB Bremen
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