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Design and failure analysis of logic-compatible multilevel ..:
, In:
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
,
Meinerzhagen, Pascal Andreas
;
Andiç, Onur
;
Treichler, Jürg
. - p. 343-346 , 2011
Link:
https://dl.acm.org/doi/10.1145/1973009.1973078
RT T1 <cTitle>Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI</cTitle>: T1 <Title>Design and failure analysis of logic-compatible multilevel gain-cell-based dram for fault-tolerant VLSI systems</Title> UL https://suche.suub.uni-bremen.de/peid=acm-1973078&Exemplar=1&LAN=DE A1 Meinerzhagen, Pascal Andreas A1 Andiç, Onur A1 Treichler, Jürg A1 Burg, Andreas Peter PB ACM YR 2011 K1 embedded memory K1 gain cell K1 high density K1 multilevel storage K1 process variations K1 read failure K1 Hardware K1 Integrated circuits K1 Semiconductor memory K1 Dynamic memory K1 Robustness K1 Hardware test SP 343 OP 346 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/1973009.1973078 DO https://dl.acm.org/doi/10.1145/1973009.1973078 SF ELIB - SuUB Bremen
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