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1
DFT logic verification through property based formal method..:
, In:
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
,
Sen, Lopamudra
;
Roy, Amit
;
Bhattacharjee, Supriya
.. - p. 33-34 , 2010
Link:
https://dl.acm.org/doi/10.5555/1998496.1998506
RT T1 <cTitle>Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design</cTitle>: T1 <Title>DFT logic verification through property based formal methods : SOC to IP</Title> UL https://suche.suub.uni-bremen.de/peid=acm-1998506&Exemplar=1&LAN=DE A1 Sen, Lopamudra A1 Roy, Amit A1 Bhattacharjee, Supriya A1 Mittra, Bijitendra A1 Roy, Subir K. PB FMCAD Inc YR 2010 K1 DFT logic K1 SOC integration K1 formal verification K1 Hardware K1 Hardware validation K1 Functional verification K1 Applied computing K1 Arts and humanities K1 Architecture (buildings) K1 Computer-aided design K1 Integrated circuits K1 Logic circuits K1 Physical sciences and engineering K1 Engineering SP 33 OP 34 LK http://dx.doi.org/https://dl.acm.org/doi/10.5555/1998496.1998506 DO https://dl.acm.org/doi/10.5555/1998496.1998506 SF ELIB - SuUB Bremen
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