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1 Ergebnisse
1
Fault-tolerant 3D clock network:
, In:
Proceedings of the 48th Design Automation Conference
,
Lung, Chiao-Ling
;
Su, Yu-Shih
;
Huang, Shih-Hsiu
.. - p. 645-651 , 2011
Link:
https://dl.acm.org/doi/10.1145/2024724.2024872
RT T1
Proceedings of the 48th Design Automation Conference
: T1
Fault-tolerant 3D clock network
UL https://suche.suub.uni-bremen.de/peid=acm-2024872&Exemplar=1&LAN=DE A1 Lung, Chiao-Ling A1 Su, Yu-Shih A1 Huang, Shih-Hsiu A1 Shi, Yiyu A1 Chang, Shih-Chieh PB ACM YR 2011 K1 3D IC K1 clock network K1 clock tree synthesis K1 fault-tolerant K1 redundant tree K1 through-silicon via K1 Hardware K1 Electronic design automation K1 Physical design (EDA) K1 Placement K1 Wire routing K1 Applied computing K1 Physical sciences and engineering K1 Engineering K1 Computer-aided design K1 Arts and humanities K1 Architecture (buildings) SP 645 OP 651 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/2024724.2024872 DO https://dl.acm.org/doi/10.1145/2024724.2024872 SF ELIB - SuUB Bremen
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