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1
Reducing off-chip memory traffic by selective cache managem..:
, In:
Proceedings of the 5th Annual Workshop on General Purpose Processing with Graphics Processing Units
,
Choi, Hyojin
;
Ahn, Jaewoo
;
Sung, Wonyong
- p. 110-119 , 2012
Link:
https://dl.acm.org/doi/10.1145/2159430.2159443
RT T1
Proceedings of the 5th Annual Workshop on General Purpose Processing with Graphics Processing Units
: T1
Reducing off-chip memory traffic by selective cache management scheme in GPGPUs
UL https://suche.suub.uni-bremen.de/peid=acm-2159443&Exemplar=1&LAN=DE A1 Choi, Hyojin A1 Ahn, Jaewoo A1 Sung, Wonyong PB ACM YR 2012 K1 GPGPU K1 cache replacement decision K1 off-chip memory traffic K1 Computer systems organization K1 Architectures K1 Parallel architectures K1 Multiple instruction, multiple data K1 Hardware K1 Integrated circuits K1 Semiconductor memory K1 Dynamic memory SP 110 OP 119 LK http://dx.doi.org/https://dl.acm.org/doi/10.1145/2159430.2159443 DO https://dl.acm.org/doi/10.1145/2159430.2159443 SF ELIB - SuUB Bremen
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